The UVD saw a refresh with the release of the Radeon HD 4000 series products. But UVD+ was also being marketed as simply UVD. UVD+ support HDCP for higher resolution video streams. AMD has also stated that the UVD component being incorporated into the GPU core only occupies 4.7 mm² in area on 65 nm fabrication process node.Ī variation on UVD, called UVD+, was introduced with the Radeon HD 3000 series. Post-processing includes denoising, de-interlacing, and scaling/resizing. UVD handles VLC/ CAVLC/ CABAC, frequency transform, pixel prediction and inloop deblocking, but passes the post processing to the shaders. Previously, neither ATI Radeon R520 series' ATI Avivo nor NVidia Geforce 7 series' PureVideo assisted front-end bitstream/entropy decompression in VC-1 and H.264 - the host CPU performed this work. MPEG-2 decode is also supported, but the bitstream/entropy decode is not performed for MPEG-2 video in hardware.
Unlike video acceleration blocks in previous generation GPUs, which demanded considerable host-CPU involvement, UVD offloads the entire video-decoder process for VC-1 and H.264 except for video post-processing, which is offloaded to the shaders.
It has context-adaptive binary arithmetic coding (CABAC) support for H.264/AVC. The decoder meets the performance and profile requirements of Blu-ray and HD DVD, decoding H.264 bitstreams up to a bitrate of 40 Mbit/s. MPEG-2 decoding is not performed within UVD, but in the shader processors. In early versions of UVD, video post-processing is passed to the pixel shaders and OpenCL kernels. The UVD technology is based on the Cadence Tensilica Xtensa processor, which was originally licensed by ATI Technologies Inc. UVD, as stated by AMD, handles decoding of H.264/AVC, and VC-1 video codecs entirely in hardware.
The UVD is based on an ATI Xilleon video processor, which is incorporated onto the same die as the GPU and is part of the ATI Avivo HD for hardware video decoding, along with the Advanced Video Processor (AVP). 5.1 Hardware video hardware technologies.
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